Request early beta access

Find PCB faults with fewer, more decisive measurements

Your PCB bring-up and debugging assistant. Import your netlist and BOM, connect your oscilloscope, and get guidance on what to measure next — with each capture bringing you closer to the faulty net or component.

KiCad, Altium, OrCAD, PADS & EDIF netlists VISA scopes, waveform files, or the built-in simulator Windows 10/11 & macOS 12+

A recreation of the YProbe main window — board tree, judged capture, comparison verdicts, and the assistant's next move.

Use the instrument already on your bench

RIGOL · bench validated SIGLENT · selected models validated KEYSIGHT · profile available TEKTRONIX · profile available

Have another SCPI oscilloscope? Upload its manufacturer's programming-guide PDF in YProbe to configure it from the documented commands and check it against your instrument. You can also import waveform files or evaluate the workflow in the simulator. See programming-guide setup or check tested models.

One connected workflow

From design files to a defensible diagnosis

YProbe connects board context, bench measurements and the decisions made between them. The result is a debugging record you can inspect, repeat and hand to another engineer.

01 · Understand the board

Reason about your circuit, not a generic schematic

Import the netlist and a CSV or Excel BOM. YProbe builds a graph of nets, components, rails, drivers and loads, then checks every suggested net and component against the design before it reaches the session.

  • KiCad, Altium, Cadence/OrCAD, PADS and EDIF
  • Power-rail, bus, driver and load classification
  • Expected signals tied to the actual board topology
Explore the bring-up workflow →
02 · Measure with confidence

Know whether the evidence deserves a verdict

YProbe configures supported scopes, reads their settings back, screens unstable probe contact and judges each parameter against the expected signal before it becomes diagnostic evidence.

  • Floating and intermittent contact blocking
  • Startup, waveform, DMM and protocol evidence
  • Real hardware, waveform import or full simulator
See measurement safeguards →
03 · Close the loop

Keep the evidence after the probe leaves the pad

Measurements, hypotheses and rework stay attached to the board. Compare sessions, identify what changed the outcome, and send a signed probe task to a technician without sending the netlist or BOM.

  • Board history and rework-aware session diff
  • Fixed, regressed and still-failing nets
  • Disclosure-minimised remote technician workflow
Explore remote debugging →
A diagnosis you can follow

From first power-on to evidence-backed root cause

Every step answers one question and makes the next measurement more valuable.

Give YProbe the board context

Load the netlist and BOM. YProbe maps rails, buses, components, drivers and loads into a graph it can reason over.

State what the board is doing

Describe the symptom in plain language: a dead rail, failed USB enumeration, missing clock or fault that appears only after warm-up.

Take the most decisive measurement

YProbe ranks the next probe point, prepares the scope or DMM, and judges the result against the expected signal and board topology.

Review the evidence trail

Hypotheses narrow after every accepted measurement until a suspect net or component is supported by a traceable chain of evidence.

Where it earns its place on the bench

Built for the faults that consume engineering time

Bring-up, intermittent failures, repair and remote triage share one problem: the evidence lives in too many places. YProbe keeps it connected.

First article

Bring up a board systematically

Verify rails, startup order, clocks and buses in a repeatable sequence instead of rebuilding a checklist for every revision.

PCB bring-up workflow →
Intermittent faults

Catch the failure that disappears on demand

Monitor droops, dropouts, glitches and recoveries over time, then carry the event into the diagnostic record.

Intermittent-fault workflow →
Repair and RMA

Connect rework to the result

Record removed parts, replacements, lifted pins and fly-wires, then see which nets were fixed, regressed or never rechecked.

See short hunting and rework evidence →
Designer ⇄ factory

Keep the technician moving without sending the design

Package signed probe tasks and expected signals while keeping the netlist, BOM and diagnostic reasoning on the designer's side.

Remote PCB debugging →
Intermittent faults

The brownout that "never happens when you're watching"

Single captures can't catch a rail that misbehaves once every few minutes. Monitor mode streams captures for as long as you need and logs a wall-clock-stamped event only when something actually crosses a threshold.

  • One debounced event per excursion — onset, worst value, recovery
  • Droop, overshoot, dropout, glitch and recovery detection
  • Thresholds from your signal specs or an auto-learned baseline
  • Excursion summaries feed straight into the AI's memory
14:02:11MONITOR+3V3_PHY · baseline learned 3.31 V (8 stable captures)
14:05:43DROOP+3V3_PHY · −310 mV for 1.8 s · worst 2.99 V
14:05:45RECOVERY+3V3_PHY · back within limits after 1.8 s
14:11:02DROPOUT+3V3_PHY · rail collapsed to 0.4 V for 220 ms
14:11:02GLITCHXTAL_25M · 2 missing cycles during dropout
14:11:03RECOVERY+3V3_PHY · restored · event sent to AI notes
Rework

Mark what you changed. YProbe keeps the score.

Swapped a resistor, pulled a cap, lifted a pin, fly-wired two pads — log it once and it stays on the record. Every PASS/FAIL is persisted per board too, so the tool can tell you what your rework actually did instead of leaving that to your memory and a spreadsheet.

  • Removed, replaced, cut at pin, fly-wired, board disconnected — timestamped, with your note
  • A fly-wire changes the board graph itself: the AI treats both nets as one node from then on
  • FIXED / REGRESSED / STILL FAILING / NEW FAILURE per net, including the ones you forgot to re-measure
  • Pull a part, watch the net pass, and YProbe ties the fix to the part that caused it
Rework log
07-21 15:41REMOVEDC47 — lifted to unload the rail
07-21 16:02REPLACEDR19 — equivalent part, value noted
07-21 16:20CUT AT PINFB1.1 — feedback path opened
07-22 09:14FLY-WIREnRST_MCU ↔ TP7 — now one node
Diff vs previous session
Example rework diff between two sessions
+3V3_PHYFAIL → PASSFIXED
+1V2_COREFAIL → PASSFIXED
USB_DPPASS → FAILREGRESSED
I2C1_SDAFAIL → FAILSTILL FAILING
SPI2_MISO— → FAILNEW FAILURE
nRST_MCUFAIL → not re-measuredCHECK

C47 removed → +3V3_PHY FAIL → PASS · high confidence · the hypothesis that blamed C47 is now confirmed

Trust is part of the measurement

Measurements you can check. Guidance you can question.

The AI can propose a hypothesis. It cannot bypass the netlist, accept a rejected capture or silently promote unvalidated hardware into evidence.

Unreliable contact cannot become a board verdict

Every capture is classified as contacted, floating, intermittent, clipped or unknown, and a cross-capture tracker requires consecutive agreement before it locks. If the verdict is floating or intermittent at the blocking confidence threshold (0.65 at full sensitivity), the capture is blocked from producing a PASS/FAIL, from entering the session record, and from reaching the AI as board evidence.

AI suggestions are constrained by the board

Every AI-returned net and component name is resolved against the imported design before it can reach the session or screen. Unknown names are rejected, so a fluent answer cannot create a probe point that is absent from the board.

Hardware support is graded, not implied by a logo

Each instrument connection is labelled simulated, bench-validated, self-tested, manually selected, unvalidated or guessed. A guessed dialect blocks automated capture until a checked programming-guide setup succeeds, the user selects a profile deliberately, or the pairing passes the bench self-test.

Early-access pricing

Start with one board. Scale to the whole lab.

Every plan includes the PCB bring-up and debugging workflow. The plan ladder changes board volume, collaboration, telemetry and deployment — not the quality of the diagnosis. Prices shown are provisional US dollars per user, billed monthly unless stated otherwise.

Evaluate

Prove the workflow on your own bench

Free trial

Two board designs, hosted diagnosis, the full simulator and a renewable seven-day evaluation key.

Request early beta access
Lab & enterprise

Standardise debugging across a team or facility

From $200 / user / mo

Multiboard systems and no product telemetry, with private endpoints, offline operation and site licensing for Enterprise.

Talk to us
Compare every early-access plan
Monthly Annual ~2 months free

Pricing is provisional while YProbe is in early access; annual figures reflect the planned ~2-months-free discount.

Trial

Evaluate at your bench's pace — hardware projects don't finish in a week.

Free

7 days · renewable

  • 2 board designs / month
  • Hosted AI diagnosis
  • Request a fresh 7-day key when it expires
  • Community support
  • Anonymized session summaries (required)
Request early beta access

Light

Solo bring-up and repair, one board at a time.

$50 / mo

billed monthly

  • 10 board designs / month
  • Hosted AI diagnosis
  • Standard support
  • Category-level fault telemetry (can be disabled)
Request early beta access

Light+

Bring your contract manufacturer into the loop.

$100 / mo

billed monthly

  • Everything in Light
  • 10 board designs / month
  • Remote debugging (designer ⇄ factory)
  • Free technician clients
  • Category-level fault telemetry (can be disabled)
Request early beta access

Pro+

High-volume benches and busy labs.

$400 / mo

billed monthly

  • Unlimited board designs
  • Multiboard systems
  • Remote debugging + free technician clients
  • No product telemetry · hosted AI processing still applies
  • Priority support
Request early beta access

Enterprise

Priced on board volume, not seats.

Contact us

annual · committed boards / month

  • Unlimited boards · site license
  • Unlimited seats per facility, per-board overage
  • Choose your LLM, private endpoint, or fully offline
  • No product telemetry · DPA & custom retention
  • Priority + dedicated support
Contact us

Your contract manufacturer debugs for free

On Light+ and above, remote debugging includes free technician clients. The CM's technician installs YProbe at no charge — only the designer needs a subscription. The technician sees probe points and expected signals, and never receives your netlist, BOM, or the AI's reasoning. Results come back signed, and verdicts are recomputed on your side.

Feature comparison across the six YProbe plans
Feature Trial Light Light+ Pro Pro+ Enterprise
Price Free · 7 days$50/mo$100/mo $200/mo$400/moContact us
Board designs / month 21010 50UnlimitedUnlimited · site license
Multiboard systems
Remote debugging (designer ⇄ factory)
AI diagnosis HostedHostedHosted HostedHostedYour LLM / private endpoint / fully offline
Data sharing Anonymized session summaries (required) Category-level fault telemetry (can be disabled) Category-level fault telemetry (can be disabled) No product telemetry No product telemetry No product telemetry · contractual (DPA)
Support CommunityStandardStandard StandardPriorityPriority + dedicated
FAQ

Frequently asked questions

Can't find your answer? Write to support@yprobe.com.

YProbe is in early access. The desktop app is built and running on real hardware; the hosted account and billing backend is what gates the public release. Request early beta access and describe your oscilloscope. We review each request before issuing a single-use invitation.

One unique netlist. Debugging the same design any number of times in a month uses one slot — ten physical units of the same board are still one design. Your monthly count resets each billing cycle.

Trial: anonymized session summaries — fault categories, measurement verdicts and fix categories, with net names anonymized. Your netlist and BOM are never uploaded as part of sharing. Light / Light+: category-level fault telemetry only (e.g. "I²C · no ACK · missing pull-up" on a "clock generator IC" — no part numbers, no net names, no design data), and you can turn it off in Settings. Pro and Pro+ send no product telemetry, but their hosted AI requests still process the structured board context needed for the diagnosis. Enterprise can use a private endpoint or run fully offline. Read the data-handling summary.

Yes, on hosted tiers — and we'd rather say so plainly than bury it. The structured board context needed for a diagnosis is processed by our server per request to run the AI analysis. Your design files themselves stay on your machine. Enterprise customers can route AI to their own private endpoint or run fully offline, so nothing leaves their network. See the exact data boundaries by plan and deployment.

You compose a signed task package; the technician runs a free YProbe client that shows probe points and expected signals — never your netlist, BOM, or the AI's reasoning. Results come back signed, and verdicts are recomputed on your side. Tasks can be conditional ("if task 3 fails, probe this next"), so the queue keeps the technician moving across time zones while you sleep.

No. All plans include hosted AI — no API keys, no per-token bills, nothing to configure. Enterprise can optionally bring their own LLM endpoint, including a local model for air-gapped labs.

A VISA connection is necessary for live control, but it is not sufficient by itself: automated capture also needs a compatible SCPI control and waveform-readout profile. Rigol and selected Siglent generations are bench-validated; Keysight, Tektronix and other Siglent profiles are available but remain labelled unvalidated until proven on hardware. Unknown instruments are blocked from automated capture unless a checked programming-guide setup succeeds, you deliberately select a profile, or the pairing passes the bench self-test. You can upload your SCPI oscilloscope's programming-guide PDF through Hardware → Configure from programming guide…. Waveform import and the simulator remain available. See the compatibility and validation matrix.

Monthly plans: yes, effective at the end of the billing period. Annual plans (including Enterprise) renew yearly.

Request early beta access

Tell us who you are and which oscilloscope you use. We review every request manually; approved participants receive a single-use invitation and the desktop build so they can evaluate a real board or the simulator.

No scope yet? Enter “Simulator” to evaluate without hardware.

We use these details to review and operate your requested beta access under Article 6(1)(b) GDPR, retain the request for up to 90 days, and do not add you to a newsletter. You may exercise your data rights at privacy@yprobe.com. Full privacy notice.