Build the board graph
Import the netlist and BOM. YProbe classifies rails, buses, components, drivers and loads and preserves the relationships between them.
PCB bring-up
A bring-up workflow that keeps every measurement connected
YProbe turns the netlist, BOM, expected signals, oscilloscope captures and engineering decisions into one traceable debugging session. You control the probe; the assistant helps you choose the measurement that matters next.
A first article rarely fails in one clean place. A rail is low because another block is loading it; a clock looks absent because the probe or timebase is wrong; a bus error is the effect of an earlier power or reset problem. YProbe treats the board as a connected system so each capture can narrow the search instead of becoming another isolated screenshot.
Four stages, one evidence trail
Describe the symptom
State what the board is doing in plain language: a dead rail, failed enumeration, missing clock, thermal drift or intermittent reset.
Take a decisive measurement
YProbe ranks the next probe point, prepares the expected signal and scope setup, then screens and judges the capture.
Review the diagnosis
Accepted measurements update the ranked hypotheses until a suspect net or component is supported by a traceable chain of evidence.
What the assistant checks during bring-up
Power and startup
Rail level, ripple, rise time, overshoot, settling and sequence order against the specification you define.
Clocks and buses
Frequency, edge quality and decoded UART, I²C or SPI traffic, tied back to channel roles inferred from the board.
Measurement integrity
Floating or intermittent probe contact, clipping, scope settings and instrument-provided measurements that contradict the sampled record.
Changes between attempts
Replaced parts, removed loads, lifted pins and fly-wires, with fixed, regressed and still-failing nets after rework.
A concrete example
A 1.2 V core rail droops when the Ethernet PHY wakes, while the 3.3 V PHY rail also fails. Because both rails share the same regulator, the next useful question is not “which random rail should I probe?” but “is the regulator switching when the load appears?” YProbe carries that relationship from the board graph into the next probe suggestion, then records the switching-node capture beside the earlier failures.
The value is not a magical answer after one measurement. It is the reduction of wasted measurements and the preservation of why each one was taken.
- Every AI-returned net or component name is validated against the imported design.
- Unreliable probe contact is blocked from becoming a PASS or FAIL.
- The instrument profile and validation grade remain visible during capture.
- The simulator exercises the same bring-up workflow without requiring a scope.
Inputs and bench options
Design context
KiCad, Altium/Protel, Altium Wire List, Cadence Telesis, Mentor/Siemens PADS-PCB and EDIF netlists, plus CSV or Excel XLSX BOMs and optional IPC-2581 layout. For legacy XLS BOMs, save as XLSX or CSV before import. See supported formats.
Measurement path
Compatible VISA oscilloscope, imported CSV/TXT waveform, DMM evidence, or the built-in simulator for a complete no-hardware evaluation.